ENEE 244 - Digital Logic Design

Number of Credits: 3
Digital Logic Design introduces the basic principles and design procedures of digital systems at the gate and intermediate chip levels for electrical engineering students. The student will acquire knowledge of gates, flip-flops, registers, counters, Karnaugh maps, PAL devices, and synchronous sequential circuit design and analysis. Students will design and analyze combinatorial logic circuits and synchronous sequential circuits. (Fall Term Only) Three hours lecture. Three Credits. Three billable hours.

Pre-requisite(s): MATH 123/MATH 124 or MATH 130.
Co-requisite(s): ENEE 245
Course Objectives: Upon successful completion of this course, students will be able to:

Convert between decimal, binary, octal, and hexadecimal number systems. (PG-1) (LG-3)
Do two-level logic minimization using Boolean algebra, Karnaugh maps, and the Quine-McCluskey tabular minimization method. (PG-1,2) (LG-2,3)
Incorporate medium scale integrated circuits, such as decoders, encoders, and multiplexers, into circuit design. (PG-1,2) (LG-2,3)
Use algorithmic state machine notation. (PG-1) (LG-3)
Design and analyze clocked sequential circuits. (PG-1,2) (LG-2,3)
Build binary memory using various types of latches and flip-flops. (PG-1,2) (LG-2,3)
Program PLA, PAL, SPLD devices. (PG-1,2) (LG-2,3)
Describe various types of memory parity and error correction algorithms. (PG-1,2) (LG-2,3)
Perform asynchronous sequential logic analysis. (PG-1,2) (LG-2,3)